Logisim Computer Architecture circuit.

Here is the list of modules used in the design:
Component name
Component properties
Component operation
4-bit adder
4-bit input A and B
Adds A and B, and outputs a 4-bit result R and a carry-out bit Co
Full adder
1-bit input A, B, and C_in
Adds A, B, and C_in, and outputs a sum bit and a carry-out bit
XOR gate
2 input bits
Outputs 1 if the inputs are different, 0 otherwise
NOT gate
1 input bit
Outputs the complement of the input bit
AND gate
2 input bits
Outputs 1 if both inputs are 1, 0 otherwise
OR gate
2 input bits
Outputs 1 if at least one input is 1, 0 otherwise
To build the 4-bit adder, we can use 4 full adders, where the carry-out of each full adder is connected to the carry-in of the next full adder. The sum bits from each full adder are combined to form the 4-bit output R, and the final carry-out bit Co is the carry-out of the last full adder.
To implement the different operations based on the control input M, we can use a decoder to select the appropriate logic gates and full adders. Here is the block diagram of the circuit:
In this diagram, the MUX selects the inputs A and B based on the value of M. When M is equal to 0, the output of the MUX is always 0. When M is equal to 1, the output of the MUX is the inverted value of A. When M is equal to 2, the output of the MUX is the value of A inverted and incremented by 1. When M is equal to 3, the output of the MUX is the sum of A and B.
The output of the MUX is then fed into the 4-bit adder sub-circuit, which adds A and B together. The output of the adder is a 4-bit bus, which represents the sum of A and B. If M is equal to 3, the carry output of the adder is also considered as part of the circuit output. Otherwise, the carry output is discarded.
Finally, the output of the circuit is fed into a splitter, which separates the carry output (if present) from the 4-bit bus representing the sum. The 4-bit bus is connected to the R output, while the carry output is connected to the Co output.
Overall, this digital system provides the specified functionality of computing various operations on 4-bit input values A and B based on a control signal M, producing a 4-bit output R and a carry output Co.
To demonstrate the functionality of the system, we can provide different input values for A and B and vary the value of M to observe the corresponding output values of R and Co.
For example, when M is set to 00, the output R should always be 0, regardless of the input values of A and B. The Co output should also be 0.
When M is set to 01, the output R should be the bitwise complement of A, and the Co output should be 0. If A is set to 0101, the output R should be 1010.
When M is set to 10, the output R should be the bitwise complement of A incremented by 1, and the Co output should depend on the result. If A is set to 0101, the output R should be 1011, and the Co output should be 1.
When M is set to 11, the output R should be the sum of A and B, and the Co output should depend on the result. If A is set to 0101 and B is set to 0011, the output R should be 10000, and the Co output should be 0. If A is set to 1111 and B is set to 0001, the output R should be 0000, and the Co output should be 1.
By testing the system with various input values and control signals, we can verify that it correctly implements the specified functionality.
a high-level diagram of the top-level circuit:
The top-level circuit takes in A, B, and M as inputs, and produces R and Co as outputs. It includes the Level-2 sub-circuit, which in turn includes the Level-1 sub-circuit. The Level-1 sub-circuit is the 1-bit Full Adder, which takes in A, B, and Ci (carry-in) as inputs and produces S (sum) and Co (carry-out) as outputs.
As the top-level circuit is the same for all the different states of M, let us provide a single structure of the top-level circuit.
The top-level circuit has four inputs and two outputs, as shown below:
The M input is a 2-bit bus, while A, B, C, and D are 4-bit buses. The R output is a 4-bit bus, and the Co output is a 1-bit bus.
Depending on the value of M, the circuit performs a different operation. Below are the brief descriptions of the circuit operation for each state of M:
M = 00: R is always 0, and Co is always 0.
M = 01: R is the logical complement of A, and Co is always 0.
M = 10: R is the 2’s complement of A, and Co depends on the result (either 0 or 1).
M = 11: R is the sum of A and B, and Co depends on the result (either 0 or 1).
Here is the cost estimation for the design:
Component name
Number of Components (N)
Component unit Cost (C)
N × C
1-bit Full Adder
4
1
4
4-bit Adder
1
4
4
2-to-4 Decoder
1
1
1
4-to-1 Multiplexer
1
1
1
NOT Gate
4
0.1
0.4
AND Gate
6
0.1
0.6
OR Gate
1
0.1
0.1